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authorStefan Tauner <stefan.tauner@alumni.tuwien.ac.at>2016-01-23 16:16:49 +0000
committerStefan Tauner <stefan.tauner@alumni.tuwien.ac.at>2016-01-23 16:16:49 +0000
commit124b7837d9c46cbc4c7c444f5d63a96d0d3b3f86 (patch)
tree2d62c23191801afaecbf98925effb8b8c7a44ab6 /jedec.c
parent41a940c641a7ddba77d04c93e01280d20a3a354a (diff)
Add a bunch of new/tested stuff and various small changes 24
Tested mainboards: OK: - ASRock G31M-GS Binary file (standard input) matches Corresponding to flashrom svn r1917.
Diffstat (limited to 'jedec.c')
-rw-r--r--jedec.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/jedec.c b/jedec.c
index 19babf9..af13876 100644
--- a/jedec.c
+++ b/jedec.c
@@ -184,13 +184,11 @@ static int probe_jedec_common(struct flashctx *flash, unsigned int mask)
else if (chip->probe_timing == TIMING_ZERO) { /* No delay. */
probe_timing_enter = probe_timing_exit = 0;
} else if (chip->probe_timing == TIMING_FIXME) { /* == _IGNORED */
- msg_cdbg("Chip lacks correct probe timing information, "
- "using default 10mS/40uS. ");
+ msg_cdbg("Chip lacks correct probe timing information, using default 10ms/40us. ");
probe_timing_enter = 10000;
probe_timing_exit = 40;
} else {
- msg_cerr("Chip has negative value in probe_timing, failing "
- "without chip access\n");
+ msg_cerr("Chip has negative value in probe_timing, failing without chip access\n");
return 0;
}